Hybrid Locking & Synchronization

Fast-path optimistic locking with fallback to pessimistic RW locks under contention

Optimizing CPU & Memory Interaction: Matrix Multiplication

Same algo, different memory access patterns, what could go wrong (or right)!

x86 Cache Control Instructions

Wherein the OS and user get more control over the L1,L2 and L3 caches, mostly for performance.

Retrieving Memory and Cache Organization

Memory, Cache levels, Cache sizes, TLB, associativity and so on

Microbenchmarking: Way more than I set out to know

RDTSC, Out-of-order execution, OS interrupts, cycles, frequency and more.

Malloc excess bytes

Space requested from malloc is a lower bound (at least or more)